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NIS5102 High Side SMART HotPlugE IC/Inrush Limiter/Circuit Breaker
The NIS5102 is a controller/FET IC that saves design time and reduces the number of components required for a complete hot swap application. It is designed for +12 V applications. This chip includes a time delay for sequencing applications. It has a dual function OVLO pin that allows multiple units to be ganged together for simultaneous turn-on and shutdown, allowing units to be operated in parallel. It allows for user selectable undervoltage and overvoltage lockout levels. Its unique current limit circuit allows for adjustable current limit levels with no external power resistor. An internal temperature limiting circuit greatly increases the reliability of this device.
Features http://onsemi.com MARKING DIAGRAM
1 5102QPxH AWLYWWG
9x9 MM, 12 PIN PLLP CASE 488AB x A WL Y WW G
* * * * * * * * * *
Integrated Power Device Power Device Thermally Protected No External Current Shunt Required Simultaneous Shutdown and Startup for Parallel Operation Enable/Timer Pin Power Good 9.0 to 18 V Input Range 10 mW Main/Mirror MOSFET Current Ratio 1000:1 Pb-Free Packages are Available
PIN CONNECTIONS
12 11 10 9 8 7 (Bottom View) 13 1 2 3 4 5 6
Typical Applications
* High Availability Systems * Electronic Circuit Breaker * 12 V Distributed Architecture
ORDERING INFORMATION
Device NIS5102QP1HT1 (Latchoff) Package Shipping
NIS5102QP1HT1G 12 Pin PLLP 1500/Tape & Reel (Latchoff) (Pb-Free) NIS5102QP2HT1 (Auto-Retry) 9x9 mm 1500/Tape & Reel 12 Pin PLLP
NIS5102QP2HT1G 12 Pin PLLP 1500/Tape & Reel (Auto-Retry) (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 3
I II II II
= 1 or 2 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free
9x9 mm 1500/Tape & Reel 12 Pin PLLP
Publication Order Number: NIS5102/D
NIS5102
VCC 13 Ccharge 5
Voltage Regulator
Charge Pump Current Limit 10, 11, 12 Source
Thermal Shutdown
2 UVLO
Undervoltage Lockout
6 Current Limit 7 Power Good
1 OVLO
Common Shutdown Overvoltage Shutdown
Enable/ Timer
Power Good
4 GND
3 Enable/Timer
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin 1 Function OVLO Description The overvoltage shutdown point is programmed by a resistor from this pin to the VCC supply. When tied together with other devices, this pin also communicates a shutdown state due to undervoltage and overtemperature reasons. All devices connected will simultaneously shutdown. Startup for this condition may be simultaneous or sequenced. A resistor from VCC to the UVLO pin adjusts the voltage at which the device will turn on. A high level signal on this pin allows the device to begin operation. Connection of a capacitor will delay turn on for timing purposes. A low input signal inhibits the operation, and communicates to any other paralleled devices (via the OVLO pin) to shutdown. This signal can also be used to reset the thermal latch. Negative input voltage to the device. This is used as the internal reference for the IC. An external capacitor is required from this pin to the source pin. This is the storage capacitor for the internal charge pump. The value of this capacitor adjusts the slew rate of the turn-on current. A small internal capacitor is included for noise filtering. A resistor (RLIMIT) tied from this pin to the source pin sets the current limit level. A high impedance signal on this pin indicates that the power device is conducting. - Source of power FET, which is also the switching node for the load. Positive input voltage to the device.
2 3
UVLO Enable/Timer
4
5
Ground Ccharge
6 7 8, 9 10, 11, 12 13
ILIMIT Power Good No Connection Source VCC
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NIS5102
MAXIMUM RATINGS (TA = 25C unless otherwise noted)
Rating Input Voltage, Operating, Steady-State (Input + to Input -) Input Voltage, Operating, Transient (Input + to Input -), 1 second Drain Voltage, Operating, Steady-State (Drain to Input -) Drain Voltage, Operating, Transient (Drain to Input -), 1 second Drain Current, Peak Continuous Current (TA = 25C, 0.5 Voltage on Power Good Pin (Pin 7) Thermal Resistance, Junction-to-Air 0.5 in2 Copper 1 in2 Copper Thermal Resistance, Junction-to-Lead Power Dissipation (TA = 25C, 0.5 in2 pad) in2 pad) Symbol Vin Vin VDD VDD IDpk IDavg Vmax7 QJA 76.5 41.2 QJL Pmax TJ TJ TL 3.2 1.4 -40 to 175 -55 to 175 235 Value -0.3 to 18 -0.3 to 25 -0.3 to 18 -0.3 to 25 20 10 20 Unit V V V V A A V C/W C/W C/W W C C C
Operating Temperature Range (Note 1) Non-Operating Temperature Range Lead Temperature, Soldering (10 Sec)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Actual maximum junction temperature is limited by an internal protection circuit and will not reach the absolute maximum temperature as specified.
ELECTRICAL CHARACTERISTICS (VCC = 12 V, RLIMIT = 36 W, CCharge = 100 pF, TJ = 25C unless otherwise noted.)
Characteristic POWER FET Delay Time (Enable High to IS = 100 mA) Charging Time (IS = 100 mA to IS = 5.0 A, RLIMIT = 36 W) ON Resistance (VCC = 12 V, IS = 5.0 A) (Note 2) Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc) Zero Gate Voltage Drain Current (VDS = 18 Vdc, VGS = 0 Vdc) Output Capacitance (VDS = 12 Vdc, VGS = 0 Vdc, f = 10 kHz) THERMAL LIMIT Shutdown Temperature (Note 3) Hysteresis (Note 3) OVER/UNDERVOLTAGE UVLO Turn-on (Input + Increasing, RextUVLO = 620 k) UVLO Hysteresis (Input + Decreasing, RextUVLO = 620 k) OVLO Turn-off (Input + Increasing, RextUVLO = 620 k) OVLO Hysteresis (Input + Decreasing, RextUVLO = 620 k) PARALLEL SHUTDOWN (Alternate Function on OVLO Pin) Device Fan-out (Minimum External Resistor Value = 2.0 kW (Note 3) Shutdown Voltage Threshold (OVLO Pin) Shutdown State Output Voltage (Isink = 2.0 mA) 2. Pulse Test: Pulse width 300 ms, duty cycle 2%. 3. Verified by design. Nfan VSD Vlow - 0.6 - - 0.8 0.3 4.0 - 0.4 Devices V V Von Vhyst Voff Vhyst 10.05 0.45 14.0 0.6 11.15 0.62 16.4 0.78 12.30 0.75 19.0 1.0 V V V V TSD Thyst 125 - 135 40 145 - C C Tdly tchg RDSon IDSS1 IDSS2 - - - - - - - 2.0 1.0 10 - - - - - 13 10 100 - ms ms mW mA mA pF Symbol Min Typ Max Unit
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NIS5102
ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V, RLIMIT = 36 W, CCharge = 100 pF, TJ = 25C unless otherwise noted.)
Characteristic CURRENT LIMIT Current Limit (Short Circuit, RLIMIT = 36 W) Current Limit (Overload, RLIMIT = 36 W) (Note 3) ENABLE/TIMER Enable Voltage (Turn-On) Enable Voltage (Turn-Off) Charging Current (Into External Capacitor) Turn-on Delay (Time from Enable High to Isource = 100 mA) CHARGE PUMP CCharge (Voltage on Pin 5 with Respect to Ground) VCC = 18 Vdc POWER GOOD Power Good High Z Signal when FET is Fully Enhanced Low Z State Output Voltage (ISink = 2 mA) Leakage Current (Vpin7 = 12 V, High Z State) Power Good Delay (Time from Power FET is Fully Enhanced to Power Good FET Changing State) TOTAL DEVICE Bias Current (Operational, VCC = 12 V) Bias Current (Non-operational, VCC = 7 V)) Minimum Operating Voltage IBias IBias Vccmin - - - 1.3 400 8.5 2.0 700 9.0 mA mA V - Vpin7 ILeak tpwrgood - - - - - 230 2.0 15 - 300 10 - - mV mA ms VCcharge - - 18 26 - - V V VENon VENoff ICharge tdelay 2.2 - 65 - - - 77 2.2 - 1.6 88 - V V mA ms ILIM1 ILIM2 3.8 7.0 4.8 7.8 5.8 8.6 A A Symbol Min Typ Max Unit
Output Current
Source Voltage Enable/Timer Threshold Input
Figure 2. Timing Diagram for External Enabled Delay
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NIS5102
TYPICAL PERFORMANCE CURVES
(TA = 25C unless otherwise noted) 14.0 13.0 UVLO TRIP POINT (V) 12.0 11.0 Turn-off 10.0 9.0 8.0 200 Turn-on OVLO TRIP POINT (V) 19.0 18.0 17.0 16.0 15.0 14.0 13.0 12.0 11.0 10.0 300 400 500 600 700 800 900 1000 9.0 100 200 300 400 500 600 700 800 900 1000 Turn-on Turn-off
RUVLO (kW)
ROVLO (kW)
Figure 3. UVLO Adjustment
100 10
Figure 4. OVLO Adjustment
Vin = 12 V Rext_ILimit = 100 W Overload di/dt (A/ms)
10 ILimit (A)
1
Short Circuit 1
0.1
0.1 10
100 RILmit (W)
1000
0.01 10
100
1000
10000
LOAD CAPACITANCE (mF)
Figure 5. Current Limit Adjustment
Figure 6. Load Capacitance vs. Output di/dt
105 95 CASE TEMPERATURE, C 85 1 sq in copper area 75 65 55 45 35 25 1.0 3.0 5.0 7.0 9.0 11 13 2 sq in copper area 1/4 sq in copper area
Device Reaching Thermal Shutdown
CONTINUOUS CURRENT, A
Figure 7. Continuous Current vs. Case Temperature (Test performed on a double-sided copper board, 1 oz)
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NIS5102
TYPICAL APPLICATION CIRCUITS AND OPERATION WAVEFORMS
(TA = 25C unless otherwise noted)
VCC ROVLO Power Good Source OVLO RUVLO UVLO En/Timer + Gnd Cdelay Current Limit Ccharge Ccharge DC-DC Converter RLIMIT + C
Figure 8. Typical Applications Circuit
Input Voltage Output Voltage
Power Good Delay
Input Voltage
Input Voltage
Power Good GND
Output Voltage
Output Current Turn on Delay
Output Current
Device Reaching Thermal Limit
Figure 9. Turn-on Waveforms for 3300 mF Load Capacitors
Figure 10. Turn-on Waveforms for Shorted Output, Latchoff Device
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NIS5102
TYPICAL APPLICATION CIRCUITS AND OPERATION WAVEFORMS (continued)
(TA = 25C unless otherwise noted)
Input Voltage Input Voltage
Power Good Power Good
Output Voltage OutputVoltage
Output Current Output Current
Device Reaching DeviceReaching Thermal Limit ThermalLimit
Figure 11. Turn-On Waveforms for Shorted Output, Auto-Retry Device
Input Voltage Input Voltage Overvoltage Overvoltage Condition condition
Output Voltage
Output Voltage Power Good Good Power
Output Current Output Current
Figure 12. Device Response During an Overvoltage Condition
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NIS5102
ROVLO
VCC
Ccharge Power Good Source RLIMIT
Ccharge ROVLO VCC
Ccharge Power Good Source RLIMIT
Ccharge
OVLO RUVLO UVLO En/Timer Current Limit Gnd Cdelay1 + + RUVLO DC-DC Converter Cdelay2
OVLO UVLO En/Timer Current Limit Gnd + Ccharge VCC Ccharge Power Good Source RUVLO VCC Ccharge Power Good Source UVLO RLIMIT Current Limit OVLO En/Timer Gnd Current Limit + RLIMIT DC-DC Converter DC-DC Converter
Figure 13. Turn-on Sequencing Using Power Good Signal
RUVLO
ROVLO
UVLO OVLO En/Timer
+
Gnd Cdelay
Figure 14. Parallel Operation / Simultaneous Turn-on and Shutdown
Input Voltage Output Voltage
Iout, Device1 Iout, Device2
Figure 15. Turn-on Waveforms for Parallel Operation
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NIS5102
OPERATING DESCRIPTION Operation The NIS5102 has a variety of shutdown and protection features that make this part extremely versatile as well as rugged. For the unit to operate, the input voltage must be within the operating range of the part which is set by the UVLO and OVLO bias resistors. The enable must also be high for operation. Current and thermal limit circuits constantly monitor the operation and will protect the unit if either of these parameters exceeds its preset limit. An additional shutdown method, is the use of the OVLO pin, which can be tied in parallel. This allows multiple units to be either operated in parallel, and will shutdown and turn on simultaneously for any fault other than an overvoltage, or it allows these hot plug devices to control independent loads, and shutdown and turn on simultaneously. Faults Once the load capacitance is charged, the SENSEFETt will become fully enhanced as long as the current does not reach the current limit threshold, or is shutdown due to an overvoltage, undervoltage or thermal fault. Both the UVLO and OVLO circuits incorporate hysteresis to assure clean turn-on and turn-offs with no chatter. The thermal latching circuit will require the input power to be recycled to resume operation after a fault. The current limit is always active, so any transient or overload will always be limited. Circuit Description
Enable/Timer
The enable/timer pin can function either as a direct enable pin, or as a time delay. In the enable mode, an open collector device is connected to this pin. When the device is in its low impedance mode, this pin is low and the operation of the chip is disabled. If a time delay is required, a capacitor is added to this pin. Figure 16 shows the equivalent circuit for the enable.
Enable/ Timer
80 mA + - Enabled
2.2 V
NIS5102
Figure 16. Enable/Timer Circuit
If a capacitor is added without an open collector device, the turn on will be delayed from the time at which the UVLO voltage is reached. If an open collector device is also used, the delay will start from the time that it goes into its high impedance state. The capacitor is charged by an internal current source. There is an inherent delay in the turn on of the hot plug device, due to the method of gate drive used. The gate of the power FET is charged through a high impedance resistor, and from the time that the gate starts charging until the time that it reaches its threshold voltage, there will be no conduction. Once the gate reaches its threshold voltage, the output current will begin a controlled ramp up phase. This delay will be added to any timing delay due to the enable/timer circuit.
Power Good
of the internal charge pump. Once the VGS of the power SENSEFET reaches around 90% of the internal charge pump output voltage, the power good will change its state from low impedance to high impedance but only after the power good delay has elapsed. Figure 9 shows the power good behavior during the startup of the NIS5102 device, an external pullup resistor from power good to VCC was used. The power good will change its state from high impedance to low impedance in the event of any fault condition such as short circuit and overvoltage.
Undervoltage Lockout
The power good circuit monitors the VGS voltage of the power SENSEFET and compares it with the output voltage
The UVLO circuit holds the chip off when the input voltage is less than the turn-on limit. It includes internal hysteresis to assure clean on/off switching. An internal divider sets the turn-on voltage level at 16 V. This voltage can be reduced by adding an external resistor from the UVLO pin to the VCC pin. The equivalent circuit is shown in Figure 17.
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NIS5102
VCC
RUVLO 400 k
Source UVLO VGS(th) = 1.15 V 40 k
3k Ground
Figure 17. Equivalent Undervoltage Lockout Circuit
The theoretical equation for the UVLO turn-on voltage is:
400 Vin * 460 RUVLO (KW) + 17.5 * Vin
ground. This will create a low pass filter with a cutoff frequency of f. The required capacitance on this pin is:
CUVLO + 1 2p * f 43 K )
RUVLO * 400 K RUVLO)400 K
The UVLO trip point voltage calculated through the theoretical formula may show small variations with respect to Figure 3, therefore it is recommended to use the formulas gotten from the UVLO characterization, which are shown below:
RUVLO (kW) + e [(UVLO ) 14.647) 3.9858]; for TJ + 25C
Overvoltage Lockout and Parallel Shutdown
where "UVLO" is the desired undervoltage lockout value, and RUVLO is the programming resistor from the UVLO pin to the VCC pin. To reduce nuisance tripping due to transients and noise spikes, a capacitor may be added from the UVLO pin to
The overvoltage lockout (OVLO) is a dual function pin. This pin will normally be biased somewhere between ground and the input voltage, due to an internal voltage divider which sets the turn-off voltage level at 22 V. This voltage level can be reduced by adding an external resistor from the OVLO pin to the VCC pin. When the input voltage reaches the programmed trip point, operation of the device is inhibited. Figure 18 shows the equivalent circuit.
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NIS5102
VCC
ROVLO 300 k
Source OVLO 7V 200 k 2M
Ground
Figure 18. Equivalent Overvoltage Lockout Circuit
The theoretical equation for the OVLO turn-on voltage is:
ROVLO (KW) + 300 Vin * 2100 21.8 * Vin
Temperature Limit
The OVLO trip point voltage calculated through the theoretical formula may show small variations with respect to Figure 4, therefore it is recommended to use the formulas gotten from the OVLO characterization, which are shown below:
ROVLO (kW) + e [(OVLO ) 5.2) 3.46]; for TJ + 25C
The temperature limit circuit senses the temperature of the Power FET and removes the gate drive if the maximum level is exceeded. For the auto-retry device, there is a nominal hysteresis of 40C for this circuit. After a thermal shutdown, the device will automatically restart when the temperature drops to a safe level as determined by the hysteresis. The latching thermal circuit can be reset either by recycling the input power, or by toggling the enable signal.
Current Limit
where "OVLO" is the desired overvoltage lockout value, and ROVLO is the programming resistor from the OVLO pin to the VCC pin. To reduce nuisance tripping due to transients and noise spikes, a capacitor may be added from the OVLO pin to ground. This will create a low pass filter with a cutoff frequency of f. The required capacitance on this pin is:
COVLO + [1 ) (8.83 E-6 * ROVLO)] 2p * f * ROVLO
This pin is also used as a common shutdown pin. In this mode, if this pin is pulled to ground, it will shutdown the chip and all chips connected to its OVLO pin. The OVLO pin has an internal switch to ground that will pull it low, whenever the device is disabled due to any fault other than an Overvoltage condition. An enable pin shutdown is not considered a fault and will not cause a common shutdown. This feature allows multiple units to turn on and off simultaneously by tying the OVLO pins together in parallel. This can be used for operating several hot plug devices in parallel, or for use with separate loads, when all devices need to startup and shutdown simultaneously.
An external resistor from the current limit pin to the source pins set the level at which the device will limit the current. The plot of resistance vs. current limit includes two curves, one for short circuit and one for overload. A short circuit condition is one in which the SENSEFET is not fully enhanced, and is therefore in a high impedance mode of operation. In this case there are many hundreds of millivolts across the drain to source pins of the SENSEFET. This occurs when the output sees a very low impedance short as well as when the capacitor is charging at turn on. In both cases there are several volts or more across the FET. An overload condition is one in which the SENSEFET is still fully enhanced and the drain to source voltage is the product of the drain current and the on resistance of the FET. The sense voltage out of the SENSEFET has a different relation to the drain current in these two conditions. The difference in current limit levels for these two cases is called DI, where:
DI + Vref RDSon
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NIS5102
For this equation, Vref is the reference voltage of the current limit circuit, and RDSon is the on resistance of the SENSEFET. For more information on this, see application note AND8140/D, "SMART HotPlugt Current Limit Function". This inherent property of the SENSEFET allows for simple dual level current limiting, in which a short circuit condition will see a lower level of limiting than will an overload. This operation will exist in start up as well as under normal operation, so the device will be able to differentiate between a short and an overload. As with all SMART HotPlug devices, the current limit will never shutdown the device. Only the thermal limit will stop the flow of current to the load. Once the current is stopped due to the thermal limit, it will remain off until input power is recycled for the latching version, or it will continuously retry to start again if it is the auto-retry version. The ILimit graph shown in Figure 5 was generated from the data of the ILimit characterization, the formula for the short circuit curve is:
RILimit (W) + 152.86 ILimit
100 Min Pad 1-in Pad THETA J(t) (C/W) 10
where "ILimit" is the desired short circuit ILimit value, and RILimit is the programming resistor from the ILimit pin to the source pin.
Turn-on Surge
During the turn-on event, there is a large amount of energy dissipated due to the linear operation of the power device. The energy rating is the amount of energy that the device can absorb before the thermal limit circuit will shut the unit down. This is very important specially for the latch off device as it determines the maximum load capacitance that the device can charge before the thermal limit shuts the device down. The calculation of this is not very simple as it depends on several factors such as the input voltage (Vin), load capacitance (CL), current limit settings (ILimit) and device's thermal transient response, therefore, it is recommended to do lab evaluations for these purposes. Figure 19 shows the device's thermal transient response for minimum pad.
1.02
for TJ + 25C
1
0.1 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
TIME (seconds)
Figure 19. Thermal Transient Response
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NIS5102
PACKAGE DIMENSIONS
PLLP-12, 9x9 mm CASE 488AB-01 ISSUE C
0.10 C 0.08 C A D B C
DIM A A1 A3 b D E e D2 E2 K L SEATING PLANE NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. COPLANARITY APPLIES TO THE LEAD, DIMENSION B, AND EXPOSED PAD. MILLIMETERS MIN MAX 1.750 1.950 0.000 0.050 0.254 REF 0.400 0.600 9.000 BSC 9.000 BSC 1.270 BSC 5.400 5.600 7.400 7.600 0.850 REF 0.850 0.950
PIN ONE LOCATION
E
4X
0.15 C TOP VIEW D2
10 X
A
SIDE VIEW
e
12 X K 12 X L
E2 e/2
12 X
b 0.10 0.05
M M
CAB C
BOTTOM VIEW
7.652 1.270 PITCH
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
I I I I I I I
(A3) A1
STYLE 1: PIN 1. OVLO 2. UVLO 3. ENABLE/TIMER 4. GND 5. CCHARGE 6. CURRENT LIMIT 7. POWER GOOD 8. N/C 9. N/C 10. SOURCE 11. SOURCE 12. SOURCE
SOLDERING FOOTPRINT*
9.305 5.652
12 X
1.054
12 X
0.551
Dimensions in mm
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NIS5102
The product described herein (NIS5102), may be covered by one or more of the following U.S. patents: 6781502; 6865063. There may be other patents pending. SMART HotPlug and SENSEFET are trademarks of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NIS5102/D

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